Abstract:

This report (thesis) presents an architectural design methodology for computing systems suitable for a class of real-time applications, characterized by a large volume of periodic real-time data input at a high rate and vector operations on the real-time data. The proposed methodology incorporates into the architectural design the notion of resource sharing as well as techniques for satisfying timing requirements. The proposed design methodology is based upon a new computing system architecture called Dynamically Reconfigurable Architecture or DRA, which is suitable for the target class of real-time applications. Its most distinguished feature is in the dynamically reconfigurable computation network, which consists of arithmetic-operation-level functional modules interconnected through a switching network or multiple data buses that can be logically reorganized for pipelined vector computations for real-time data. The computation network is logically configured to form one or more arithmetic pipelines before vector operations are initiated and remains unchanged during the vector operations.