Abstract:

This paper addresses the need for a framework that combines software and hardware implementation level optimiza- tion to improve the energy efficiency of sparse quantized deep neural networks (DNN). The proposed joint neural architecture optimization approach explores the best design in each paradigm, from Python simulation to hardware-FPGA implementation. As a result, it reaches the best power and area requirements in FPGA implementation. We evaluate our method on a real-time signal-processing DNN model and find that it achieves 1.7× improvements in power and 40× in area compared to the baseline implementation of the same model. Our findings demonstrate the effectiveness of the proposed framework in optimizing power and area requirements for DNNs, which is important for IoT and edge devices where resource constraints are acute.